To reduce the cost and increase the performance of electronic computers, it is desirable to place as many electronic circuits in as small a region as possible in order to reduce the distance over which electrical signals must travel from one circuit to another. This can be achieved by fabricating on a given area of a semiconductor chip as many electronic circuits as feasible with a given fabrication technology. Typically, these dense chips are disposed on the surface of a substrate in a side by side arrangement with space left there between to provide regions for electrical conductors for electrical interconnection of the chips. The chip contact locations can be electrically connected to substrate contact locations by means of wires bonded between the chip contact locations and the substrate contact locations. Alternatively a TAB tape (which is a flexible dielectric layer having a plurality of conductors disposed thereon) can be used for this electrical connection. Alternatively, the semiconductor chips can be mounted in a flip-chip configuration wherein an array of contact locations on the semiconductor chips is aligned with and electrically connected to an array of contact locations on the substrate by means of solder mounds disposed between corresponding chip and substrate contact locations. The side by side arrangement of electronic devices is not the most dense configuration which can be achieved.
The most dense packaging configuration for semiconductor chips, in particular for memory chips, such as DRAMS, SRAMS, Flash Eproms and the like, may be obtained through the construction of a solid cube of semiconductor chips. The difficult problem to solve for such a cube is providing for electrical connections to the chips. The electrical connections must include power supply, data and address lines and the like.
Prior art shows that it is possible to construct dense packages of stacked semiconductor wafers or chips. The major problems are that of interconnecting the chips electrically and that of solving the problem of thermal dissipation. Chips are generally stacked in orthogonal rectangular or cubic structures.
As used herein, an orthogonal rectangular or cubic package refers to a package wherein either square or rectangular chips are stacked directly on top of each other with the edges thereof of adjacent chips aligned.
The electrical connections are handled generally in three manners: (1) Fabricate vias through the semiconductor structures to facilitate interconnections; (2) metallization is carried up to and past the edge of the chips and are also placed on the sides of the stack; (3) chips are bonded on carriers which bring electrical connections past the edges of the chip. The carriers are in turn stacked in orthogonal rectangular or cubic structures.
Generally, the problem of thermal dissipation is either not addressed or is handled by conduction through the structures to the environment.
IBM Technical Disclosure Bulletin, Vol. 14 (9), 2561 (1972) "Bubble Domain 3-Dimensional Magneto-Optic Memory", H. Chang, describes a non-orthogonal stack of chips whose faces are offset so as to allow laser access to one row of pads on each chip. No plan for electrical contact, I/O for power, board mounting or cooling is provided.
U.S. Pat. No. 4,500,905, "Stacked Semiconductor Device with Sloping Sides", describes a non-orthogonal package wherein semiconductor layer fabricated upon one another, are metallized to the edge, and contacts are made on the face of a solid composed of stacked semiconductors. However, the face of the solid is slanted, making the stack into a pyramid rather than a parallelepiped shape. Additional semiconductors are fabricated mounted on the four sides of the pyramidal structure. No cooling means are provided. No means are provided for electrical connection to a board or higher-level package.
It is an object of the present invention to provide an electronic device structure wherein at least one electronic device has at least one edge with at least one contact location thereon. The edge of the electronic device having the contact location is disposed against a substrate having at least one contact location. The electronic device subtends a non-orthogonal angle with respect to the substrate.
It is another object of the present invention to provide a non-orthogonal electronic device package having a plurality of electronic devices in a stack wherein each electronic device has an edge having at least one contact location. The edges with the contact locations thereon are arranged in a stepped or staircase arrangement.
In another more particular aspect of the present invention, the stepped region of the chip stack is disposed against a substrate having a plurality of contact locations thereon for electrical connection to corresponding contact locations on the stepped surface of the chip stack.
These and other objects, features and advantages of the present invention will be more readily apparent to those of skill in the art from the following specification and the appended drawings.